This invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a very Large Scale Integrated (LSI) MOS type semiconductor device to which miniaturization processing of submicron order is implemented and a manufacturing method thereof.
According as semiconductor devices have been integrated to high degree, components or elements become small in dimensions. Marked progress has been shown in respect of both the miniaturization processing technique and the structure of components.
In the field of the miniaturization processing, the miniaturization processing having a resolution of the minimum pattern of 0.6 .mu.m can be carried out under the present circumstances. However, even if conventional MOS FETs are manufactured by using such a miniaturization processing technique, the size of field region is limited to 1.2 .mu.m even at the minimum due to bird's beaks which occur during the selective oxidation. In addition, the sizes of the source and drain regions are limited even at the minimum due to bird's beak in the selective oxidation. In addition, the sizes of the source and drain regions are limited even at the minimum to a value obtained by adding 0.2 .mu.m to the diameter of the contact hole, i.e., 0.6 .mu.m+0.2 .mu.m=0.8 .mu.m in consideration of an electric withstand voltage across the side surface of the contact hole and the gate electrode, etc. When an alignment accuracy is taken into account, the limit value is further increased by approximately 0.15 .mu.m. Accordingly, even if the alignment accuracy is disregarded, the conventional MOS FET is required to be 4.6 .mu.m in dimensions even at the minimum. As just described above, the conventional MOS FET has a problem that the size thereof is greately ruled by factors, e.g., the dimension of the field region, the dimension of contact hole, and the alignment accuracy, etc., rather than it is prescribed by the sizes of the gate, or the source and drain regions, etc., so that the development of the miniaturization processing technique does not directly lead to the miniaturization of a MOS FET.
Further, in regard to the structure of transistors, if the gate region is reduced for miniaturization or fining of MOS FET, there arise problems that the short channel effect becomes conspicuous, that the hot electron effect is difficult to disregard. For relaxing the short channel effect, the thickness of the gate oxide film must be thinned. For preventing the hot electron effect, it is required to adopt an LDD (Lightly Doped Drain) structure in which a low concentration impurity diffused region is formed in a channel region between high concentration impurity diffused regions serving as the source/ the drain and a region directly below the gate, or similar structure. However, employment of such a structure leads to problems that the reliability and/or drivability of MOS FET are lowered, that the manufacturing process becomes complicated, and that the manufacturing margin is narrowed, resulting in lowering productivity.